Jobs
FPGA RTL Design Engineer at UST
FPGA RTL Design Engineer at UST, found 20 days ago on Telegram. Based in Bengaluru, India. The company takes applications on its own page.
Embedded engineer
Telegram
20 days ago
UST
UST is hiring experienced FPGA RTL design engineers to work on FPGA design and validation.
What you would do
- Design FPGA RTL
- Work with Verilog and SystemVerilog
- Handle AXI protocols
- Carry out post-silicon validation
- Debug hardware issues
What they ask for
- 5+ years of experience
- FPGA design skills
- Verilog/SystemVerilog knowledge
- AXI protocols knowledge
- Embedded systems experience
- Notice period of 0-30 days
About this job
- Job
- FPGA RTL Design Engineer
- Category
- Embedded engineer
- Company
- UST
- Location
- Bengaluru, India
- Posted
- on Telegram, 19 October 2026
- How to apply
- By email to the recruiter, with your CV
How to apply to this embedded engineer job
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The recruiter published this post and takes applications on the company's own page. PileSkip shows a summary written by AI from the post, so check the details when you apply; the link goes to a signed-in account. Post #4441.